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HT45R35V C/R to F Type 8-Bit OTP MCU
Technical Document
* Tools Information * FAQs * Application Note - HA0075E MCU Reset and Oscillator Circuits Application Note
Features
* Operating voltage: * All instructions executed in one or two instruction
fSYS=4MHz: 2.2V~5.5V fSYS=8MHz: 3.3V~5.5V
* 16 bidirectional I/O lines * Two external interrupt inputs shared with I/O lines * 8-bit programmable timer/event counter with
cycles
* 14-bit table read instruction * Four-level subroutine nesting * Bit manipulation instruction * 63 powerful instructions * Low voltage reset function * Integrated DC 24V to 5V LDO regulator * Buzzer and filament 5V to 24V output level shifter * 24-bit shift register/latch for VFD panel driving 24
overflow interrupt and 7-stage prescaler
* External RC oscillation converter * On-chip crystal and RC oscillator * Watchdog Timer * 12 capacitor/resistor sensor input * 204814 program memory * 1208 data memory RAM * Power Down and Wake-up function reduce power
grid/segment outputs
* Integrated 3-line serial VFD interface for
grid/segment display control
* 52-pin QFP package type
consumption
* Up to 0.5ms instruction cycle with 8MHz system clock
at VDD=5V
General Description
The HT45R35V is a C/R to F Type with 8-bit high performance RISC architecture microcontroller designed especially for VFD applications. The usual Holtek MCU features such as power down and wake-up functions, oscillator options, etc. combine to ensure user applications require a minimum of external components. The device is specifically designed for VFD applications that interface directly to VFD panels. The benefits of integrated C/R to F functions, in addition to low power consumption, high performance, I/O flexibility and low-cost, enhance the versatility of these devices to suit a wide range of VFD application possibilities such as household appliance timers, various consumer products, subsystem controllers, other home appliances etc.
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Block Diagram
P A 0 /IN T 0 /R C 1 P A 1 /IN T 1 /R C 2
STACK0 P ro g ra m ROM P ro g ra m C o u n te r STACK1
In te rru p t C ir c u it IN T C
TM RC TM R M U X P r e s c a le r S y s te m C lo c k
P A 2 /T M R /R C 3
W DTS In s tr u c tio n R e g is te r MP M U X D a ta M e m o ry W D T P r e s c a le r WDT M
U X
S y s te m
C lo c k /4
PAC PA
PORT A
In s tr u c tio n D ecoder ALU T im in g G e n e ra to r
MUX
PA PA PA PA PA PA PB PB PB PB
0 /IN 1 /IN 2 /T 3 /R 5 /R 7 /R 0~ 3 /B 5 /S 6 /C
T0 T1 MR C4 C1 C1 PB Z T L
/R C 1 RC /R C 2 /R C 3 , P A 4 /R C 9 0 , P A 6 /R C 1 1 2
OSC
PBC S ta tu s PB PB
PORT B
S h ifte r
2 I, P B 4 /F 1 ROBE K , P B 7 /D A T A
OSC2
OS RE VD VS S
C1 S D
ACC
VFD D r iv e r
VF F1 BZ BZ O
D 0~VFD 23 O O
LDO R e g u la to r M U X
VCC VO S y s te m S y s te m C lo c k C lo c k /4
T im e r A
T im e r B A n a lo g S w itc h
RC
O s c illa tio n O u tp u t
R C 1~R C 12 RCOUT IN RREF CREF
RC O s c illa tio n
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HT45R35V
Pin Assignment
VF V V V V V V V V V O 52515049484746454443424140 1 2 3 4 5 6 7 8 10 11 12 13 14151617181920212223242526 9 H T45R 35V 5 2 Q F P -A S 0 1 2 3 4 5 6 7 8 9 0 VFD VFD VFD VFD VFD VFD VFD VFD VFD VFD VFD VFD VFD 11 12 13 14 15 16 17 18 19 20 21 22 23 V
D1 FD FD FD FD FD FD FD FD FD FD V VS
CR RR P A 0 /IN P A 1 /IN P A 2 /T P RC T0 T1 MR A3 /R /R /R /R R R R O
P
NC B0 EF EF IN UT C1 C2 C3 C4 C5 C6 C7
39 38 37 36 35 34 33 32 31 30 29 28 27
F1O BZO BZO VCC OSC1 OSC2 D S 7 /R 6 /R 5 /R 4 /R 8 C12 C11 C10 C9
VD RE PA PA PA PA RC
Pin Description
Pin Name I/O Options Description Bidirectional 8-bit I/O port. Each pin can be configured as a wake-up input via configuration options. Software instructions determine if the pin is a CMOS output or Schmitt trigger input. Pull-high resistors can be added to the each pin via a configuration option. Pins PA0 and PA1 are pin-shared with external interrupt input pins INT0 and INT1, respectively. Configuration options determine the interrupt enable/disable and the interrupt low/high trigger type. Pins PA2 is pin-shared with the external timer input pins TMR. Each Pin of PA0~PA3 and PA4~PA7 are pin-shared with RC1~RC4 and RC9~RC12 respectively via configuration options. RC1~RC4 and RC9~RC12 are capacitor or resistor connection pins. Bidirectional 1-bit I/O port. Software instructions determine if the pin is a CMOS output or Schmitt trigger input. Pull-high resistors can be added to the each pin via a configuration option. These two pads are internal I/O and not bound out. PB3~PB7 are used to control the VFD driver interface. Configuration options determine which pins on the port have pull-high resistors. The pins should only be used as outputs and as VFD interface pins and not as normal I/O pins. Capacitor or resistor connection pins Capacitor or resistor connection pin to RC OSC Oscillation input pin Reference resistor connection pin Reference capacitor connection pin High voltage filament output signal
PA0/INT0/RC1 PA1/INT1/RC2 PA2/TMR/RC3 PA3/RC4 PA4/RC9 PA5/RC10 PA6/RC11 PA7/RC12
I/O
Pull-high* Wake-up
PB0 PB1~PB2 PB3/BZI PB4/F1 PB5/STROBW PB6/CLK PB7/DATA RC5~RC8 RCOUT IN RREF CREF F1O
I/O 3/4
Pull-high* 3/4
I/O
Pull-high*
II/O I I O O O
3/4 3/4 3/4 3/4 3/4 3/4
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Pin Name BZO BZO VO VCC VFD0~VFD23 RES VSS VDD OSC1 OSC2 Note: I/O O 3/4 3/4 O I 3/4 3/4 I O Options 3/4 3/4 3/4 3/4 3/4 3/4 3/4 Description High voltage buzzer complement output signals LDO regulator output High voltage positive power supply for driving the VFD filament, F1O, BZO and BZO outputs. An external 10uF capacitor is recommended to be connected to ground on the PCB to reduce surge voltages. High voltage grid/segment output for VFD panel Schmitt trigger reset input. Active low Negative power supply, ground Positive power supply OSC1, OSC2 are connected to an RC network or Crystal determined by a configuration option, for the internal system clock. In the case of the RC oscillator, OSC2 can be used to monitor the system clock. Its frequency is 1/4 system clock.
Crystal or RC
1. *All pull-high resistors are controlled by an option bit. 2. Pin PB3~PB7 are five internal pins only and not bound out and its port control register must setup this pin as an output. 3. PB3~PB7 individual pins can be selected to have a pull-high resistor.
Absolute Maximum Ratings
Supply Voltage ...........................VSS-0.3V to VSS+6.0V Input Voltage..............................VSS-0.3V to VDD+0.3V VCC Supply Voltage.....................................12V to 24V IOH Total ............................................................-100mA Storage Temperature ............................-50C to 125C Operating Temperature...........................-40C to 85C IOL Total ..............................................................150mA Total Power Dissipation .....................................500mW
Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
D.C. Characteristics
Symbol Parameter Test Conditions VDD VCC 3/4 3V 5V 5V 3V 5V 3V 5V 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 Conditions fSYS=4MHz fSYS=8MHz No load, fSYS=4MHz Min. 2.2 3.3 3/4 3/4 3/4 3/4 3/4 3/4 3/4 0 Typ. 3/4 3/4 1 3 4 3/4 3/4 3/4 3/4 3/4 Max. 5.5 5.5 2 5 8 5 10 1 2 0.3VDD
Ta=25C Unit V V mA mA mA mA mA mA mA V
VDD
Operating Voltage Operating Current (Crystal OSC, RC OSC) Operating Current (Crystal OSC, RC OSC) Standby Current (WDT Enabled) Standby Current (WDT Disabled) Input Low Voltage for I/O Ports, TMR, INT0 and INT1
IDD1
IDD2
No load, fSYS=8MHz
ISTB1
No load, system HALT
ISTB2
No load, system HALT 3/4
VIL1
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Symbol VIH1 VIL2 VIH2 VLVR IOL Parameter Input High Voltage for I/O Ports, TMR, INT0 and INT1 Input Low Voltage (RES) Input High Voltage (RES) Low Voltage Reset I/O, RREF and CREF Sink Current I/O, RREF and CREF Source Current Pull-high Resistance 5V RPL VO VCC IOUT DVLNR DVLDR VDRO ICC1 3V RC1~RC12 Pull-low Resistance 5V LDO Output Voltage 3/4 Test Conditions VDD VCC 3/4 3/4 3/4 3/4 3V 5V 3V 5V 3V 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 For VCC5V VIN=(VOUT+0.1V) to 24V, IOUT=1mA IOUT=100mA to 20mA, COUT=10pF IOUT=1mA Conditions 3/4 3/4 3/4 LVR enabled VOL=0.1VDD Min. 0.7VDD 0 0.9VDD 2.7 4 10 VOH=0.9VDD 3/4 3/4 3/4 3/4 3/4 3/4 -2 -5 20 10 20 10 4.7 12 10 TBD TBD 25 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 VOL= 0.1VCC 2.5 TBD VOH= 0.9VCC -15 TBD VOL= 0.1VCC 15 TBD Typ. 3/4 3/4 3/4 3.0 8 20 -4 -10 60 30 60 30 5.0 3/4 3/4 0.06 0.16 30 70 TBD 70 TBD 130 TBD 90 TBD Max. VDD 0.4VDD VDD 3.3 3/4 3/4 3/4 3/4 100 50 100 50 5.3 24 3/4 TBD TBD 35 110 TBD 110 TBD 180 TBD 140 TBD Unit
V V V V mA mA mA mA kW kW kW kW V V mA %/V %/mA mV mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA
IOH
RPH
VFD, F1O, BZO and BZO Output 3/4 Supply Voltage Maximum LDO Output Current Line Regulation Load Regulation Dropout Voltage Logic Operating Current 1 3/4 3/4 3/4 3/4 5V
18V No load, VFD outputs, all 24V output low, CLK=100kHz 18V No load, VFD outputs, all 24V output high, CLK=100kHz 18V No load, BZI input 50kHz 24V 18V
ICC2
Logic Operating Current 2
5V
ICC3
Buzzer Operating Current
5V
ICC4
Filament Operating Current
5V 24V
No load, F1 input 50kHz
ISTB
Standby Current (LDO Always On, WDT Enable/Disable)
18V 5V 24V No load
65 105 (TBC) (TBC) TBD 5.0 TBD -30 TBD 30 TBD TBD 3/4 3/4 3/4 3/4 3/4 3/4
IOL2
18V F1O Sink Current 5V 24V 18V F1O Source Current 5V 24V 18V BZO/BZO Sink Current 5V 24V
IOH2
IOL3
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Symbol Parameter Test Conditions VDD VCC 18V BZO/BZO Source Current 5V 24V IOL4 18V Grid/Segment Sink Current 5V 24V IOH4 18V Grid/Segment Source Current 5V 24V VOH= 0.9VCC VOL= 0.1VCC Conditions VOH= 0.9VCC Min. -15 TBD 2.5 TBD -6 TBD Typ. -30 TBD 5.0 TBD -12 TBD 3/4 3/4 3/4 3/4 Max. 3/4 Unit mA mA mA mA mA mA
IOH3
A.C. Characteristics
Symbol Parameter System Clock (Crystal OSC, RC OSC) Timer I/P Frequency Test Conditions VDD 3/4 3/4 3/4 3/4 3V 5V tWDT1 tWDT2 tRES tSST tINT tLVR tPHL, tPLH Watchdog Time-out Period (WDT RC OSC) Watchdog Time-out Period (System Clock/4) 3V Without WDT prescaler 5V 3/4 Without WDT prescaler 3/4 Wake-up from HALT 3/4 3/4 VCC=15V VCC=15V VCC=15V VCC=15V VCC=15V VCC=15V VCC=15V 3/4 3/4 3/4 VCC=15V VCC=15V VCC=15V VCC=15V 8 3/4 1 3/4 1 0.25 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 17 1024 3/4 1024 3/4 1 100 100 40 10 10 10 75 3/4 40 35 8 33 3/4 3/4 3/4 3/4 2 200 200 80 20 20 20 150 20 83 70 3/4 Conditions 2.2V~5.5V 3.3V~5.5V 2.2V~5.5V 3.3V~5.5V 3/4 3/4 Min. 400 400 0 0 45 32 11 Typ. 3/4 3/4 3/4 3/4 90 65 23 Max. 4000 8000 4000 8000 180 130 46
Ta=25C Unit kHz kHz kHz kHz ms ms ms ms tSYS ms tSYS ms ms ns ns ns ns ns ns ns ns ns ns MHz
fSYS
fTIMER
tWDTOSC Watchdog Oscillator Period
External Reset Low Pulse Width 3/4 System Start-up Timer Period Interrupt Pulse Width Low Voltage Reset Time Propagation Delay Time (Clock to VFD Output) Propagation Delay Time (Strobe to VFD Output) Output Transition Time Data Setup Time Setup Time (Clock to Strobe) Hold Time (Data to Clock) Hold Time (Clock to Strobe) Clock Input Rise or Fall Time Clock Pulse Width Strobe Pulse Width 3/4 3/4 3/4 3/4 3/4 3/4 3/4
tTHL, tTLH tSU tCS tH tSC tr, tf tWC tWL fmax
Maximum Clock Input Fre3/4 quency
Note: *tSYS=1/fSYS Rev. 1.00 6 January 15, 2009
HT45R35V
A.C. Waveforms
1 /fm CLK 50% VSS tS
U ax
VO
tH
tW
C
tW
C
VO DATA VSS tP VFDn tT
LH LH
tP
HL
VO VSS
HL
tT
Data Propagation Delays, Setup and Hold Times
VO DATA tC
S
VSS tS
C
CLK
50% tW
L
VO VSS VO
STROBE
VSS tP
LH
, tP
HL
VO VFDn VSS
Strobe Propagation Delays, Setup and Hold Times
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Functional Description
Execution Flow The system clock for the microcontroller is derived from either a crystal or an RC oscillator. The system clock is internally divided into four non-overlapping clocks. One instruction cycle consists of four system clock cycles. Instruction fetching and execution are pipelined in such a way that a fetch takes an instruction cycle while decoding and execution takes the next instruction cycle. However, the pipelining scheme causes each instruction to effectively execute in a cycle. If an instruction changes the program counter, two cycles are required to complete the instruction. Program Counter - PC The program counter, PC controls the sequence in which the instructions stored in program ROM are executed and its contents specify full range of program memory. After accessing a program memory word to fetch an instruction code, the contents of the program counter are
T1 T2 T3 T4 T1 T2
incremented by one. The program counter then points to the memory word containing the next instruction code. When executing a jump instruction, a conditional skip execution, loading the PCL register, a subroutine call, an initial reset, an internal interrupt, an external interrupt or return from a subroutine, the PC manipulates the program transfer by loading the address corresponding to each instruction. The conditional skip is activated by instructions. Once the condition is met, the next instruction, fetched during the current instruction execution, is discarded and a dummy cycle replaces it to get the proper instruction. Otherwise the program will proceed with the next instruction. The lower byte of the program counter, PCL is a readable and writable register. Moving data into the PCL performs a short jump. The destination must be within the current Program Memory Page. When a control transfer takes place, an additional dummy cycle is required.
T3 T4 T1 T2 T3 T4
S y s te m
C lo c k
O S C 2 ( R C o n ly ) PC PC PC+1 PC+2
F e tc h IN S T (P C ) E x e c u te IN S T (P C -1 )
F e tc h IN S T (P C + 1 ) E x e c u te IN S T (P C )
F e tc h IN S T (P C + 2 ) E x e c u te IN S T (P C + 1 )
Execution Flow Program Counter *10 0 0 0 0 0 *9 0 0 0 0 0 *8 0 0 0 0 0 *7 0 0 0 0 0 *6 0 0 0 0 0 *5 0 0 0 0 0 *4 0 0 0 0 1 *3 0 0 1 1 0 *2 0 1 0 1 0 *1 0 0 0 0 0 *0 0 0 0 0 0
Mode Initial Reset External Interrupt 0 External Interrupt 1 Timer/Event Counter Overflow External RC Oscillation Converter Interrupt Skip Loading PCL Jump, Call Branch Return from Subroutine
Program Counter+2 *10 #10 S10 *9 #9 S9 *8 #8 S8 @7 #7 S7 @6 #6 S6 @5 #5 S5 @4 #4 S4 @3 #3 S3 @2 #2 S2 @1 #1 S1 @0 #0 S0
Program Counter Note: *10~*0: Program Counter bits #10~#0: Instruction code bits S10~S0: Stack register bits @7~@0: PCL bits
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Program Memory The program memory is used to store the program instructions which are to be executed. It also contains data, table, and interrupt entries, and is organized into 204814 bits, addressed by the program counter and table pointer. Certain locations in the program memory are reserved for special usage:
* Location 000H * Location 010H
This location is reserved for the external RC oscillation converter interrupt service program. If an interrupt results from an external RC oscillation converter, and if the interrupt is enabled and the stack is not full, the program begins execution at this location.
* Table location
This area is reserved for program initialisation. After a device reset, the program always begins execution at location 000H.
* Location 004H
This location is reserved for the external interrupt 0 service program. If the INT0 input pin is activated, the interrupt is enabled and the stack is not full, the program begins execution at this location.
* Location 008H
This location is reserved for the external interrupt 1 service program. If the INT1 input pin is activated, the interrupt is enabled and the stack is not full, the program begins execution at this location.
* Location 00CH
This location is reserved for the Timer/Event Counter interrupt service program. If a Timer interrupt results from a Timer/Event Counter overflow, and the interrupt is enabled and the stack is not full, the program begins execution at this location.
000H 004H 008H 00CH 010H D e v ic e In itia liz a tio n P r o g r a m E x te rn a l In te rru p t 0 E x te rn a l In te rru p t 1 T im e r /E v e n t C o u n te r O v e r flo w E x te r n a l R C O s c illa tio n C o n v e rte r In te rru p t P ro g ra m M e m o ry
Any location in the program memory can be used as a look-up table. The instructions TABRDC [m] (the current page, 1 page=256 words) and TABRDL [m] transfer the contents of the lower-order byte to the specified data memory, and the higher-order byte to TBLH. Only the destination of the lower-order byte in the table is well-defined, the other bits of the table word are transferred to the lower portion of TBLH, and the remaining 2 bits are read as 0. The Table Higher-order byte register, TBLH, is read only. The table pointer, TBLP, is a read/write register, which indicates the table location. Before accessing the table, the location must be placed in TBLP. The TBLH register is read only and cannot be restored. If the main routine and the ISR (Interrupt Service Routine) both employ the table read instruction, the contents of the TBLH in the main routine are likely to be changed by the table read instruction used in the ISR and errors may occur. Therefore, using the table read instruction in the main routine and also in the ISR should be avoided. However, if the table read instruction has to be used in both the main routine and in the ISR, the interrupt should be disabled prior to the table read instruction execution. The interrupt should not be re-enabled until TBLH has been backed up. All table related instructions require two cycles to complete the operation. These areas may function as normal program memory depending upon the requirements. Stack Register - STACK This is a special part of the memory which is used to save the contents of the program counter only. The stack is organised into 4-levels and is neither part of the data nor part of the program space, and is neither readable nor writable. The activated level is indexed by the stack pointer, SP and is neither readable nor writeable. At a subroutine call or interrupt acknowledgment, the contents of the program counter are pushed onto the stack. At the end of a subroutine or an interrupt routine, signaled Table Location
n00H nFFH 700H 7FFH
L o o k - u p T a b le ( 2 5 6 w o r d s )
L o o k - u p T a b le ( 2 5 6 w o r d s ) 1 4 - B its N o te : n ra n g e s fro m 0 to 7
Program Memory
Instruction TABRDC [m] TABRDL [m]
*10 P10 1
*9 P9 1
*8 P8 1
*7 @7 @7
*6 @6 @6
*5 @5 @5
*4 @4 @4
*3 @3 @3
*2 @2 @2
*1 @1 @1
*0 @0 @0
Table Location Note: *10~*0: Table location bits @7~@0: Table pointer bits Rev. 1.00 9 January 15, 2009 P10~P8: Current program counter bits
HT45R35V
by a return instruction, RET or RETI, the program counter is restored to its previous value from the stack. After a device reset, the stack pointer will point to the top of the stack. If the stack is full and a non-masked interrupt takes place, the interrupt request flag will be recorded but the acknowledgment will be inhibited. When the stack pointer is decremented, by RET or RETI, the interrupt will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily. In a similar case, if the stack is full and a CALL is subsequently executed, stack overflow occurs and the first entry will be lost as only the most recent 4 return addresses are stored. Data Memory - RAM The data memory has a capacity of 1468 bits. The data memory is divided into two functional groups: special function registers and general purpose data memory (1208). Most are read/write, but some are read only. The general purpose data memory, addressed from 28H to 7FH at Bank 0 and from 40H to 5FH at Bank 1, is used for data and control information under instruction commands. All of the data memory areas can handle arithmetic, logic, increment, decrement and rotate operations directly. Except for some dedicated bits, each bit in the data memory can be set and reset by the SET [m].i and CLR [m].i bit manipulation instructions. They are also indirectly accessible through the memory pointer registers (MP0;01H, MP1;02H). Bank 1 must be addressed indirectly using the memory pointer MP1 and the indirect addressing register IAR1. Any direct addressing or any indirect addressing using MP0 and IAR0 will always result in data from Bank 0 being accessed. Indirect Addressing Register The method of indirect addressing allows data manipulation using memory pointers instead of the usual direct memory addressing method where the actual memory address is defined. Any action on the indirect addressing registers will result in corresponding read/write operations to the memory location specified by the corresponding memory pointers. This device contains two indirect addressing registers known as IAR0 and IAR1 and two memory pointers MP0 and MP1. Note that these indirect addressing registers are not physically implemented and that reading the indirect addressing registers indirectly will return a result of 00H and writing to the registers indirectly will result in no operation. The two memory pointers, MP0 and MP1, are physically implemented in the data memory and can be manipulated in the same way as normal registers providing a convenient way with which to address and track data. When any operation to the relevant indirect addressing
00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 7FH 40H 5FH G e n e ra l P u rp o s e D a ta M e m o ry (8 8 B y te s ) :U nused R e a d a s "0 0 " TM RAH TM RAL RCOCCR TM RBH TM RBL RCOCR IN T C 1 ASCR0 ASCR1 ASCR2 PA PAC PB PBC S p e c ia l P u r p o s e D a ta M e m o ry TM R TM RC In d ir e c t A d d r e s s in g R e g is te r 0 MP0 In d ir e c t A d d r e s s in g R e g is te r 1 MP1 BP ACC PCL TBLP TBLH W DTS STATUS IN T C 0
RAM
M a p p in g B a n k 0
G e n e ra l P u rp o s e D a ta M e m o ry (3 2 B y te s )
RAM
M a p p in g B a n k 1
RAM Mapping
registers is carried out, the actual address that the microcontroller is directed to is the address specified by the related memory pointer. Bit 7 of the memory pointers are not implemented. However, it must be noted that when the memory pointers in this device is read, a value of 1 will be read.
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Bank Pointer - BP When using instructions to access the general purpose data memory in Bank 0 or Bank 1, it is necessary to ensure that the correct area is selected. The general purpose data memory is sub-divided into two banks, Bank 0 and Bank 1 for this device. Selecting the correct data memory area is achieved by using the bank pointer. If data in Bank 0 or Bank 1 is to be accessed, the BP must be set to the values 00H or 01H respectively, however, it must be noted that data in Bank 1 can only be addressed indirectly using the MP1 memory pointer and the IAR1 indirect addressing register. Any direct addressing or any indirect addressing using MP0 and IAR0 will always result in data from Bank 0 being accessed. The data memory is initialized to Bank 0 after a reset, except for the WDT time-out reset in the Power Down Mode, in which case, the data memory bank remains unchanged. It should be noted that the special function data memory is not affected by the bank selection, which means that the special function registers can be accessed from within either Bank 0 or Bank 1. Accumulator The accumulator is closely related to ALU operations. It is also mapped to location 05H of the data memory and can carry out immediate data operations. The data movement between two data memory locations must pass through the accumulator. Arithmetic and Logic Unit - ALU This circuit performs 8-bit arithmetic and logic operations. The ALU provides the following functions:
* Arithmetic operations - ADD, ADC, SUB, SBC, DAA * Logic operations - AND, OR, XOR, CPL * Rotation - RL, RR, RLC, RRC * Increment and Decrement - INC, DEC * Branch decision - SZ, SNZ, SIZ, SDZ ....
The ALU not only saves the results of a data operation but also changes the status register. Status Register - STATUS This 8-bit register contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PDF), and watchdog time-out flag (TO). It also records the status information and controls the operation sequence. With the exception of the TO and PDF flags, bits in the status register can be altered by instructions like most other registers. Any data written into the status register will not change the TO or PDF flag. In addition operations related to the status register may give different results from those intended. The TO flag can be affected only by a system power-up, a WDT time-out or executing the CLR WDT or HALT instruction. The PDF flag can be affected only by executing a HALT or CLR WDT instruction or a system power-up. The Z, OV, AC and C flags generally reflect the status of the latest operations. In addition, on entering the interrupt sequence or executing the subroutine call, the status register will not be pushed onto the stack automatically. If the contents of the status are important and if the subroutine can corrupt the status register, precautions must be taken to save it properly.
Bit No. 0
Label C
Function C is set if the operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction. AC is set if the operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared. Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared. OV is set if the operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared. PDF is cleared by system power-up or executing the CLR WDT instruction. PDF is set by executing the HALT instruction. TO is cleared by system power-up or executing the CLR WDT or HALT instruction. TO is set by a WDT time-out. Unused bit, read as 0 Status (0AH) Register
1 2 3 4 5 6~7
AC Z OV PDF TO 3/4
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Interrupt The devices provides two external interrupts, one internal 8-bit timer/event counter interrupt and one external RC oscillation converter interrupt. The interrupt control register 0, INTC0, and interrupt control register 1, INTC1, both contain the interrupt control bits that are used to set the enable/disable and interrupt request flags. Once an interrupt subroutine is serviced, all the other interrupts will be blocked, as the EMI bit will be cleared automatically. However this scheme may prevent further interrupt nesting. Other interrupt requests may happen during this interval but only the interrupt request flag is recorded. If a certain interrupt requires servicing within the service routine, the EMI bit and the corresponding bit of the INTC0 and INTC1 registers may be set to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the Stack Pointer is decremented. If immediate service is desired, the stack must be prevented from becoming full. All interrupts have a wake-up capability. As an interrupt is serviced, a control transfer occurs by pushing the program counter onto the stack, followed by a branch to a subroutine at a specified location in the program memory. Only the program counter is pushed onto the stack. If the contents of the accumulator or status register are altered by the interrupt service program, this may corrupt the desired control sequence, therefore their contents should be saved in advance. External interrupts are triggered by an edge transition on pins INT0 or INT1. A configuration option enables these pins as interrupts and selects if they are active on high to low or low to high transitions. If active their related interrupt request flag, EIF0; bit 4 in INTC0, and EIF1; bit 5 in INTC0, will be set. After the interrupt is enabled, the stack is not full, and the external interrupt is active, a subroutine call to location 04H or 08H will occur. The interrupt request flags, EIF0 or EIF1, and the EMI bit will all be cleared to disable other interrupts. The internal Timer/Event Counter interrupt is initialised by setting the Timer/Event Counter interrupt request flag, TF; bit 6 in INTC0. A timer interrupt will be generated when the timer overflows. After the interrupt is enabled, and the stack is not full, and the TF bit is set, a subroutine call to location 0CH will occur. The related interrupt request flag, TF, is reset, and the EMI bit is cleared to disable other interrupts. The external RC oscillation converter interrupt is initialized by setting the external RC oscillation converter interrupt request flag, RCOCF; bit 4 of INTC1. This is caused by a Timer A or Timer B overflow. When the interrupt is enabled, and the stack is not full and the RCOCF bit is set, a subroutine call to location 10H will occur. The related interrupt request flag, RCOCF, will be reset and the EMI bit cleared to disable further interrupts. During the execution of an interrupt subroutine, other interrupt acknowledgments are held until the RETI instruction is executed or the EMI bit and the related interrupt control bit are set to 1, if the stack is not full. To return from the interrupt subroutine, a RET or RETI instruction may be invoked. RETI will set the EMI bit to enable an interrupt service, but RET will not. Function Controls the master (global) interrupt (1= enabled; 0= disabled) Controls the external interrupt 0 (1= enabled; 0= disabled) Controls the external interrupt 1 (1= enabled; 0= disabled) Controls the Timer/Event Counter interrupt (1= enabled; 0= disabled) External interrupt 0 request flag (1= active; 0= inactive) External interrupt 1 request flag (1= active; 0= inactive) Internal Timer/Event Counter request flag (1= active; 0= inactive) Unused bit, read as 0 INTC0 (0BH) Register
Bit No. 0 1 2 3 4 5 6 7
Label EMI EEI0 EEI1 ETI EIF0 EIF1 TF 3/4
Bit No. 0 1~3, 5~7 4
Label
Function
ERCOCI Controls the external RC oscillation converter interrupt (1= enabled; 0= disabled) 3/4 Unused bit, read as 0
RCOCF External RC oscillation converter request flag (1= active; 0= inactive) INTC1 (1EH) Register
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Interrupts, occurring in the interval between the rising edges of two consecutive T2 pulses, will be serviced on the latter of the two T2 pulses, if the corresponding interrupts are enabled. In the case of simultaneous requests the following table shows the priority that is applied. These can be masked by resetting the EMI bit. Interrupt Source External Interrupt 0 External Interrupt 1 Timer/Event Counter Overflow External RC Oscillation Converter Interrupt Interrupt Priority The EMI, EEI0, EEI1, ETI and ERCOCI bits are all used to control the enable/disable status of interrupts. These bits prevent the requested interrupt from being serviced. Once the interrupt request flags, TF, RCOCF, EIF1 and EIF0, are all set, they remain in the INTC1 or INTC0 registers respectively until the interrupts are serviced or cleared by a software instruction. It is recommended that a program does not use the CALL subroutine within the interrupt subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately in some applications. If only one stack is left and enabling the interrupt is not well controlled, the original control sequence may be damaged once the CALL is executed in the interrupt subroutine. Oscillator Configuration Various oscillator options offer the user a wide range of functions according to their various application requirements. Two types of system clocks can be selected while various clock source options for the Watchdog Timer are provided for maximum flexibility. All oscillator options are selected through the configuration options. The two methods of generating the system clock are:
* External crystal/resonator oscillator * External RC oscillator
C1 Rp OSC1 Rf Ca In te r n a l O s c illa to r C ir c u it
Cb C2 OSC2
T o in te r n a l c ir c u its
Priority 1 2 3 4
Vector 04H 08H 0CH 10H
N o te : 1 . R p is n o r m a lly n o t r e q u ir e d . 2 . A lth o u g h n o t s h o w n O S C 1 /O S C 2 p in s h a v e a p a r a s itic c a p a c ita n c e o f a r o u n d 7 p F .
Crystal/Resonator Oscillator resonator types, to ensure oscillation and accurate frequency generation, it may be necessary to add two small value external capacitors, C1 and C2. The exact values of C1 and C2 should be selected in consultation with the crystal or resonator manufacturers specification. The external parallel feedback resistor, Rp, is normally not required but in some cases may be needed to assist with oscillation start up. Internal Ca, Cb, Rf Typical Values @ 5V, 25C Ca TBD Cb TBD Rf TBD
Oscillator Internal Component Values Crystal Oscillator C1 and C2 Values Crystal Frequency 12MHz 8MHz 4MHz 1MHz Note: C1 TBD TBD TBD TBD C2 TBD TBD TBD TBD CL TBD TBD TBD TBD
1. C1 and C2 values are for guidance only. 2. CL is the crystal manufacturer specified load capacitor value.
Crystal Recommended Capacitor Values Resonator C1 and C2 Values Resonator Frequency 3.58MHz 1MHz 455kHz C1 TBD TBD TBD C2 TBD TBD TBD
One of these two methods must be selected using the configuration options. More information regarding the oscillator is located in Application Note HA0075E on the Holtek website. External Crystal/Resonator Oscillator The simple connection of a crystal across OSC1 and OSC2 will create the necessary phase shift and feedback for oscillation, and will normally not require external capacitors. However, for some crystals and most
Note:
C1 and C2 values are for guidance only.
Resonator Recommended Capacitor Values
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External RC Oscillator Using the external system RC oscillator requires that a resistor, with a value between 24kW and 1.5MW, is connected between OSC1 and VDD, and a capacitor is connected to ground. The generated system clock divided by 4 will be provided on OSC2 as an output which can be used for external synchronization purposes. Note that as the OSC2 output is an NMOS open-drain type, a pull high resistor should be connected if it to be used to monitor the internal frequency. Although this is a cost effective oscillator configuration, the oscillation frequency can vary with VDD, temperature and process variations and is therefore not suitable for applications where timing is critical or where accurate oscillator frequencies are required.For the value of the external resistor ROSC refer to the Holtek website for typical RC Oscillator vs. Temperature and VDD characteristics graphics. Note that it is the only microcontroller internal circuitry together with the external resistor, that determine the frequency of the oscillator. The external capacitor shown on the diagram does not influence the frequency of oscillation.
V R
OSC DD
Watchdog Timer - WDT The WDT clock can be sourced from its own dedicated internal oscillator (WDT oscillator), or from the or instruction clock, which is the system clock divided by 4. The choice is determined via a configuration option. The WDT timer is designed to prevent a software malfunction or sequence from jumping to an unknown location with unpredictable results. The Watchdog Timer can be disabled by a configuration option. If the Watchdog Timer is disabled, any executions related to the WDT result in no operation. The WDT clock source is first divided by 256. If the internal WDT oscillator is used ,this gives a nominal time-out period of approximately 17ms at 5V. This time-out period may vary with temperatures, VDD and process variations. By using the WDT prescaler, longer time-out periods can be realised. Writing data to the WS2, WS1, WS0 bits in the WDTS register, can give different time-out periods. If WS2, WS1 and WS0 are all equal to 1, the division ratio will be 1:128, and the maximum time-out period will be 2.1s at 5V. If the internal WDT oscillator is disabled, the WDT clock may still come from the instruction clock and operate in the same manner except that in the Power Down state the WDT will stop counting and lose its protecting purpose. The high nibble and bit 3 of the WDTS can be used for user defined flags. If the device operates in a noisy environment, using the internal WDT oscillator is the recommended choice, since the HALT instruction will stop the system clock. WS2 0 0 0 0 1 1 1 1 WS1 0 0 1 1 0 0 1 1 WS0 0 1 0 1 0 1 0 1 Division Ratio 1:1 1:2 1:4 1:8 1:16 1:32 1:64 1:128
OSC1 470pF
fS
YS
/4 N M O S O p e n D r a in
OSC2
External RC Oscillator Watchdog Timer Oscillator The WDT oscillator is a fully self-contained free running on-chip RC oscillator with a typical period of 65ms at 5V requiring no external components. When the device enters the Power Down Mode, the system clock will stop running but the WDT oscillator continues to free-run and to keep the watchdog active. However, to preserve power in certain applications the WDT oscillator can be disabled via a configuration option.
WDTS (09H) Register
S y s te m
C lo c k /4 W D T P r e s c a le r O p tio n S e le c t W DT OSC 8 - b it C o u n te r 7 - b it C o u n te r
8 -to -1 M U X W D T T im e - o u t
W S0~W S2
Watchdog Timer
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The WDT overflow under normal operation will generate a chip reset and set the status bit TO. But in the Power Down mode, the overflow will generate a warm reset, where only the Program Counter and Stack Pointer are reset to zero. To clear the contents of the WDT, including the WDT prescaler, three methods can be used; an external reset (a low level to RES), a software instruction and a HALT instruction. The software instruction includes CLR WDT instruction and the instruction pair - CLR WDT1 and CLR WDT2. Of these two types of instruction, only one can be active depending on the configuration option - CLR WDT times selection option. If the CLR WDT is selected, i.e. CLRWDT times equal one, any execution of the CLR WDT instruction will clear the WDT. In the case that CLR WDT1 and CLR WDT2 are chosen, i.e. CLRWDT times equal two, these two instructions must be executed to clear the WDT; otherwise, the WDT may reset the chip as a result of a time-out. Power Down Operation The Power Down mode is initialized by the HALT instruction and results in the following...
* The system oscillator will be turned off but the WDT
set causes a device initialisation and the WDT overflow performs a warm reset. After the TO and PDF flags are examined, the reason for the device reset can be determined. The PDF flag is cleared by a system power-up or executing the CLR WDT instruction and is set when a HALT instruction is executed. The TO flag is set if a WDT time-out occurs, and causes a wake-up that only resets the program counter and stack pointer; the other registers maintain their their original status. The port A and interrupt methods of wake-up can be considered as a continuation of normal execution. Each bit in port A can be independently selected by configuration options to wake-up the device. When awakened from an I/O port stimulus, the program will resume execution at the next instruction. If it is awakened due to an interrupt, two sequences may happen. If the related interrupt is disabled or the interrupt is enabled but the stack is full, the program will resume execution at the next instruction. If the interrupt is enabled and the stack is not full, the regular interrupt response takes place. If an interrupt request flag is set to 1 before entering the Power Down Mode, the wake-up function of the related interrupt will be disabled. Once a wake-up event occurs, it takes 1024 tSYS (system clock periods) to resume normal operation. A dummy period is therefore inserted after wake-up. If the wake-up results from an interrupt acknowledgment, the actual interrupt subroutine execution will be delayed by one or more cycles. If the wake-up results in the next instruction execution, this will be executed immediately after the dummy period is finished. To minimise power consumption, all the I/O pins should be carefully managed before entering the Power Down mode.
oscillator keeps running, if the internal WDT oscillator has been selected as the WDT source clock.
* The contents of the on chip RAM and registers remain
unchanged.
* The WDT and WDT prescaler will be cleared and will
resume counting, if the internal WDT oscillator has been selected as the WDT source clock
* AlloftheI/Oportswillmaintaintheiroriginalstatus. * The PDF flag is set and the TO flag is cleared.
The system can leave the Power Down mode by means of an external reset, an interrupt, an external falling edge signal on port Aor a WDT overflow. An external re-
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Reset There are three ways in which a reset can occur:
* RES reset during normal operation * RES reset during HALT * WDT time-out reset during normal operation
The functional unit device reset status are shown below. Program Counter Interrupt Prescaler WDT Timer/Event Counter Input/Output Ports Stack Pointer 000H Disable Clear Clear. After master reset, WDT begins counting Off Input mode Points to the top of the stack
A WDT time-out, when the device is in the Power Down mode, is different from other device reset conditions, in that it can perform a warm reset that resets only the Program Counter and the Stack Poiner, leaving the other circuits in their original state. Some registers remain unchanged during other reset conditions. Most registers are reset to their initial condition when the reset conditions are met. By examining the PDF and TO flags, the program can distinguish between the different device reset types. TO 0 u 0 1 1 PDF 0 u 1 u 1 RESET Conditions RES reset during power-up RES reset during normal operation RES wake-up HALT WDT time-out during normal operation WDT wake-up HALT
HALT W DT
RES
W a rm
R eset
OSC1
SST 1 0 - b it R ip p le C o u n te r S y s te m R eset
C o ld R eset
Note: u means unchanged To guarantee that the system oscillator is started and stabilised, the SST or System Start-up Timer, provides an extra-delay of 1024 system clock pulses when the system is reset (power-up, WDT time-out or RES reset) or when the system awakens from a Power Down state.
V
Reset Configuration
DD
V
DD
0 .0 1 m F 100kW RES 0 .1 m F 100kW RES 10kW 0 .1 m F
When a system reset occurs, the SST delay is added during the reset period. Any wake-up the Power Down mode will enable the SST delay. An extra option load time delay is added during a system reset (power-up, WDT time-out during normal mode or a RES reset).
B a s ic Reset C ir c u it
H i-n o is e Reset C ir c u it
Reset Circuit
VDD RES S S T T im e - o u t C h ip R eset tS
ST
Note:
Most applications can use the Basic Reset Circuit as shown, however for applications with extensive noise, it is recommended to use the Hi-noise Reset Circuit.
Reset Timing Chart
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The states of the registers is summarized in the table. Register MP0 MP1 BP ACC Program Counter TBLP TBLH WDTS STATUS INTC0 TMR TMRC PA PAC PB PBC ASCR0 ASCR1 ASCR2 INTC1 TMRAH TMRAL RCOCCR TMRBH TMRBL RCOCR Note: Reset (Power-on) -xxx xxxx -xxx xxxx xxxx xxxx xxxx xxxx 000H xxxx xxxx --xx xxxx 0000 0111 --00 xxxx -000 0000 xxxx xxxx 00-0 1000 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 ---- 1111 --11 1111 ---0 ---0 xxxx xxxx xxxx xxxx 0000 1--xxxx xxxx xxxx xxxx 1xxx --00 WDT Time-out (Normal Operation) -uuu uuuu -uuu uuuu xxxx xxxx uuuu uuuu 000H uuuu uuuu --uu uuuu 0000 0111 --1u uuuu -000 0000 xxxx xxxx 00-0 1000 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 ---- 1111 --11 1111 ---0 ---0 xxxx xxxx xxxx xxxx 0000 1--xxxx xxxx xxxx xxxx 1xxx --00 RES Reset (Normal Operation) -uuu uuuu -uuu uuuu xxxx xxxx uuuu uuuu 000H uuuu uuuu --uu uuuu 0000 0111 --uu uuuu -000 0000 xxxx xxxx 00-0 1000 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 ---- 1111 --11 1111 ---0 ---0 xxxx xxxx xxxx xxxx 0000 1--xxxx xxxx xxxx xxxx 1xxx --00 RES Reset (HALT) -uuu uuuu -uuu uuuu xxxx xxxx uuuu uuuu 000H uuuu uuuu --uu uuuu 0000 0111 --01 uuuu -000 0000 xxxx xxxx 00-0 1000 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 ---- 1111 --11 1111 ---0 ---0 xxxx xxxx xxxx xxxx 0000 1--xxxx xxxx xxxx xxxx 1xxx --00 WDT Time-out (HALT)* -uuu uuuu -uuu uuuu xxxx xxxx uuuu uuuu 000H uuuu uuuu --uu uuuu uuuu uuuu --11 uuuu -uuu uuuu uuuu uuuu uu-u uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu ---- uuuu --uu uuuu ---u ---u uuuu uuuu uuuu uuuu uuuu u--uuuu uuuu uuuu uuuu uuuu --uu
* means warm reset u means unchanged x means unknown - stands for unimplemented If the configuration options select PA0~PA7 to be RC inputs, then the corresponding bits in the PA data register and PA control register will be unimplemented and will be read as zero. If the configuration options select PA0~PA7 to be normal I/O pins, then bit 0~bit3 in the ASCR0 and ASCR1 registers will be unimplemented and will be read as zero.
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Timer/Event Counter An 8-bit timer/event counter, known as Timer/Event Counter, is implemented in the microcontroller. The Timer/Event Counter contains an 8-bit programmable count-up counter whose clock may come from an external source or from the system clock. Using the external clock input allows the user to count external events, measure time internals or pulse widths, or generate an accurate time base. Using the internal clock allows the user to generate an accurate time base. There are 2 registers related to the Timer/Event Counter, TMR and TMRC. Two physical registers are mapped to the TMR location; writing to TMR places the start value of the Timer/Event Counter in a preload register while reading TMR retrieves the contents of the Timer/Event Counter. The TMRC is a timer/event counter control register, which defines the timer operating conditions. The TM0, TM1 bits define the operating mode. The event count mode is used to count external events, which
S y s te m C lo c k 7 - S ta g e P r e s c a le r 8 -1 M U X TPSC 2~TPSC0 TM R TE TM 1 TM 0 TON P u ls e W id th M e a s u re m e n t M o d e C o n tro l 8 - B it T im e r /E v e n t C o u n te r (T M R ) O v e r flo w to In te rru p t f IN
T
means the clock source comes from an external TMR pin. The timer mode functions as a normal timer with the clock source coming from the fINT clock. The pulse width measurement mode can be used to measure the high or low level duration of an external signal on the TMR pin. The counting is based on the fINT clock source. In the event counting or timer mode, once the timer/event counter starts counting, it will count from the current contents in the Timer/Event Counter to FFH. Once overflow occurs, the counter is reloaded from the Timer/Event Counter preload register and an interrupt request flag TF; bit 5 of INTC0, is generated at the same time. In the pulse width measurement mode, with the TON and TE bits equal to one, once the TMR pin has received a transient from low to high, or high to low if the TE bit is 0, it will start counting until the TMR pin returns to its original level and resets the TON bit. The measured result will remain in the Timer/Event Counter even if the activated transient occurs again. Therefore, only a single shot measurement can be made. The TON bit must be set again by software for further measurements
D a ta B u s TM 1 TM 0 8 - B it T im e r /E v e n t C o u n te r R e lo a d P r e lo a d R e g is te r
Timer/Event Counter Bit No. Label Function To define the prescaler stages, TPSC2, TPSC1, TPSC0= 000: fINT=fSYS 001: fINT=fSYS/2 010: fINT=fSYS/4 011: fINT=fSYS/8 100: fINT=fSYS/16 101: fINT=fSYS/32 110: fINT=fSYS/64 111: fINT=fSYS/128 To define the TMR active edge of the timer/event counter (0=active on low to high; 1=active on high to low) To enable or disable timer counting (0=disabled; 1=enabled) Unused bit, read as 0 To define the operating mode, TM1, TM0= 01=Event count mode (external clock) 10=Timer mode (internal clock) 11=Pulse width measurement mode 00=Unused TMRC (0EH) Register
0~2
TPSC0~TPSC2
3 4 5
TE TON 3/4
6 7
TM0 TM1
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to be made. Note that, in this operating mode, the Timer/Event Counter starts counting not according to the logic level but according to the transient edges. In the case of a counter overflow, the counter is reloaded from the Timer/Event Counter preload register and issues an interrupt request just like the other two modes. To enable a counting operation, the Timer ON bit, TON; bit 4 of TMRC, should be set to 1. In the pulse width measurement mode, the TON will be cleared automatically after the measurement cycle is completed. But in the other two modes, the TON can only be reset by instructions. The Timer/Event Counter overflow is one of the wake-up sources. No matter what the operation mode is, writing a 0 to ETI can disable the interrupt service. If the Timer/Event Counter is switched off, then writing data to the Timer/Event Counter preload register will also directly reload that data to the Timer/Event Counter. But if the Timer/Event Counter is already running, data written to it will only be loaded into the Timer/Event Counter preload register. The Timer/Event Counter will continue to operate until an overflow occurs. When the Timer/Event Counter is read, the clock will be blocked to avoid errors. As clock blocking may results in a counting error, this must be taken into consideration by the programmer. Bit0~Bit2 of the TMRC register can be used to define the pre-scaling stages of the internal clock source of the Timer/Event Counter. Bit No. 0~2 3 4 Label 3/4 3/4 Unused bit, read as 0 Undefined bit, this bit can read/write External RC Oscillation Converter An external RC oscillation mode is implemented in the device. The RC oscillation converter contains two 16-bit programmable count-up counters. The RC oscillation converter is comprised of the TMRAL, TMRAH, TMRBL, TMRBH registers when the RCO bit, bit 1 of RCOCR register, is 1. The RC oscillation converter Timer B clock source may come from an external RC oscillator. The Timer A clock source comes from the system clock or from the system clock/4, determined by the RCOCCR register. There are six registers related to the RC oscillation converter, i.e., TMRAH, TMRAL, RCOCCR, TMRBH, TMRBL and RCOCR. The internal timer clock is the input to TMRAH and TMRAL, the external RC oscillation is the input to TMRBH and TMRBL. The OVB bit, bit 0 of the RCOCR register, decides whether Timer A overflows or Timer B overflows, then the RCOCF bit is set and an external RC oscillation converter interrupt occurs. When the RC oscillation converter mode Timer A or Timer B overflows, the RCOCON bit is reset to 0 and stops counting. Writing to TMRAH/TMRBH places the start value in Timer A/Timer B while reading TMRAH/TMRBH obtains the contents of Timer A/Timer B. Writing to TMRAL/TMRBL only writes the data into a low byte buffer. However writing to TMRAH/TMRBH will write the data and the contents of the low byte buffer into Function
RCOCON Enable or disable external RC oscillation converter counting (0=disabled; 1=enabled) Define the Timer A clock source, RCOM2, RCOM1, RCOM0= 000=System clock 001=System clock/4 RCOM0 010=Unused RCOM1 011=Unused RCOM2 100=Unused 101=Unused 110=Unused 111=Unused RCOCCR (22H) Register
5 6 7
Bit No. 0
Label OVB
Function In the RC oscillation converter mode, this bit is used to define the timer/event counter interrupt, which comes from Timer A overflow or Timer B overflow. (0=Timer A overflow; 1=Timer B overflow) Define RC oscillation converter mode. (0=Disable RC oscillation converter mode; 1=Enable RC oscillation converter mode) Unused bit, read as 0 4-bit read/write registers for user defined. RCOCR (25H) Register
1 2~3 4~7
RCO 3/4 RW
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S y s te m S y s te m C lo c k C lo c k /4 S1 S2 O VB=0 T im e r A RCOCON O VB=1 T im e r B RC OSC O u tp u t R esetR C O C O N E x te rn a l R C O s c illa tio n C o n v e r te r In te r r u p t
External RC Oscillation Converter
the Timer A/Timer B (16-bit) simultaneously. Timer A/Timer B is changed by writing to TMRAH/TMRBH but writing to TMRAL/TMRBL will keep the Timer A/Timer B unchanged. Reading TMRAH/TMRBH will also latch the TMRAL/TMRBL into the low byte buffer to avoid false timing problem. Reading TMRAL/TMRBL returns the contents of the low byte buffer. Therefore, the low byte of Timer A/Timer B can not be read directly. It must read TMRAH/TMRBH first to ensure that the low byte contents of Timer A/Timer B are latched into the buffer. The resistor and capacitor form an oscillation circuit and input to TMRBH and TMRBL. The RCOM0, RCOM1
and RCOM2 bits of RCOCCR define the clock source of Timer A. It is recommended that the clock source of Timer A uses the system clock or the instruction clock. If the RCOCON bit, bit 4 of RCOCCR, is set to 1, Timer A and Timer B will start counting until Timer A or Timer B overflows, the timer/event counter will then generate an interrupt request flag which is RCOCF; bit 4 of INTC1. The Timer A and Timer B will stop counting and will reset the RCOCON bit to 0 at the same time. If the RCOCON bit is 1, TMRAH, TMRAL, TMRBH and TMRBL cannot be read or written.
External RC oscillation converter mode example program - Timer A overflow: clr RCOCCR mov a, 00000010b mov RCOCR,a clr intc1.4 mov a, low (65536-1000) mov tmral, a mov a, high (65536-1000) mov tmrah, a mov a, 00h mov tmrbl, a mov a, 00h mov tmrbh, a mov a, 00110000b mov RCOCCR, a p10: clr wdt snz intc1.4 jmp p10 clr intc1.4 ; Enable External RC oscillation mode and set Timer A overflow ; Clear External RC Oscillation Converter interrupt request flag ; Give timer A initial value ; Timer A count 1000 time and then overflow
; Give timer B initial value
; Timer A clock source=fSYS/4 and timer on
; Polling External RC Oscillation Converter interrupt request flag ; Clear External RC Oscillation Converter interrupt request flag ; Program continue
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Analog Switch There are 12 analog switch lines in the device for RC1~RC12, and three corresponding Analog Switch Control registers, which are ASCR0, ASCR1 and ASCR2. If the configuration options select PA0~PA3 to be normal I/O pins, then the corresponding bit 0~bit3 bits in the ASCR0 register will be unimplemented and will be read as zero. Bit No. 0 Label AS1ON Function Defines RC1 analog switch is on or off. AS1ON= 0=Analog switch 1 on, and RC1 is disconnected to pull-low 1=Analog switch 1 off, and RC1 is connected to pull-low or not according ASPLON0 register Defines RC2 analog switch is on or off. AS2ON= 0=Analog switch 2 on, and RC2 is disconnected to pull-low 1=Analog switch 2 off, and RC2 is connected to pull-low or not according ASPLON0 register Defines RC3 analog switch is on or off. AS3ON= 0=Analog switch 3 on, and RC3 is disconnected to pull-low 1=Analog switch 3 off, and RC3 is connected to pull-low or not according ASPLON1 register Defines RC4 analog switch is on or off. AS4ON= 0=Analog switch 4 on, and RC4 is disconnected to pull-low 1=Analog switch 4 off, and RC4 is connected to pull-low or not according ASPLON1 register Defines RC5 analog switch is on or off. AS5ON= 0=Analog switch 5 on, and RC5 is disconnected to pull-low 1=Analog switch 5 off, and RC5 is connected to pull-low or not according ASPLON2 register Defines RC6 analog switch is on or off. AS6ON= 0=Analog switch 6 on, and RC6 is disconnected to pull-low 1=Analog switch 6 off, and RC6 is connected to pull-low or not according ASPLON2 register Defines RC7 analog switch is on or off. AS7ON= 0=Analog switch 7 on, and RC7 is disconnected to pull-low 1=Analog switch 7 off, and RC7 is connected to pull-low or not according ASPLON3 register Defines RC8 analog switch is on or off. AS8ON= 0=Analog switch 8 on, and RC8 is disconnected to pull-low 1=Analog switch 8 off, and RC8 is connected to pull-low or not according ASPLON3 register ASCR0 (1AH) Register
1
AS2ON
2
AS3ON
3
AS4ON
4
AS5ON
5
AS6ON
6
AS7ON
7
AS8ON
If the configuration options select PA4~PA7 to be normal I/O pins, then the corresponding bit 0~bit3 bits in the ASCR1 register will be unimplemented and will be read as zero. Bit No. 0 Label AS9ON Function Defines RC9 analog switch is on or off. AS9ON= 0=Analog switch 9 on, and RC9 is disconnected to pull-low 1=Analog switch 9 off, and RC9 is connected to pull-low or not according ASPLON4 register
1
Defines RC10 analog switch is on or off. AS10ON= AS10ON 0=Analog switch 10 on, and RC10 is disconnected to pull-low 1=Analog switch 10 off, and RC10 is connected to pull-low or not according ASPLON4 register Defines RC11 analog switch is on or off. AS11ON= AS11ON 0=Analog switch 11 on, and RC11 is disconnected to pull-low 1=Analog switch 11 off, and RC11 is connected to pull-low or not according ASPLON5 register Defines RC12 analog switch is on or off. AS12ON= AS12ON 0=Analog switch 12 on, and RC12 is disconnected to pull-low 1=Analog switch 12 off, and RC12 is connected to pull-low or not according ASPLON5 register 3/4 Unused bit, read as 0 ASCR1 (1BH) Register
2
3 4~7
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If the configuration options select PA0~PA7 to be normal I/O pins, then the corresponding bits in the ASCR2 register, bit 0, bit1, bit4 and bit5, must be set to 0 to disable the RC1/RC2, RC3/RC4, RC9/RC10 or RC11/RC12 pull-low resistors. These bits are set to 0 or 1 by software. Bit No. Label Function
0
Defines RC1 pull-low and RC2 pull-low is non-pull-low. ASPLON0= 0=RC1 and RC2 are non-pull-low ASPLON0 1=RC1 and RC2 are pull-low or not according RC1, RC2 analog is on or off. RC1/RC2 is connected to pull-low when ASPLON0=1 and AS1ON/AS2ON analog switch is off. Defines RC3 pull-low and RC4 pull-low is non-pull-low. ASPLON1= 0=RC3 and RC4 are non-pull-low ASPLON1 1=RC3 and RC4 are pull-low or not according RC3, RC4 analog is on or off. RC3/RC4 is connected to pull-low when ASPLON1=1 and AS3ON/AS4ON analog switch is off. Defines RC5 pull-low and RC6 pull-low is non-pull-low. ASPLON2= 0=RC5 and RC6 are non-pull-low ASPLON2 1=RC5 and RC6 are pull-low or not according RC5, RC6 analog is on or off. RC5/RC6 is connected to pull-low when ASPLON2=1 and AS5ON/AS6ON analog switch is off. Defines RC7 pull-low and RC8 pull-low is non-pull-low. ASPLON3= 0=RC7 and RC8 are non-pull-low ASPLON3 1=RC7 and RC8 are pull-low or not according RC7, RC8 analog is on or off. RC7/RC8 is connected to pull-low when ASPLON3=1 and AS7ON/AS8ON analog switch is off. Defines RC9 pull-low and RC10 pull-low is non-pull-low. ASPLON4= 0=RC9 and RC10 are non-pull-low ASPLON4 1=RC9 and RC10 are pull-low or not according RC9, RC10 analog is on or off. RC9/RC10 is connected to pull-low when ASPLON4=1 and AS9ON/AS10ON analog switch is off. Defines RC11 pull-low and RC12 pull-low is non-pull-low. ASPLON5= 0=RC11 and RC12 are non-pull-low ASPLON5 1=RC11 and RC12 are pull-low or not according RC11, RC12 analog is on or off. RC11/RC12 is connected to pull-low when ASPLON5=1 and AS11ON/AS12ON analog switch is off. 3/4 Unused bit, read as 0 ASCR2 (1CH) Register
ASCR0 ASCR1 ASCR2
1
2
3
4
5
6~7
RC1 RC2 RC3 RC4 RC5 RC6 T .G .1 ~ T .G .1 2 RC1~R C12 RC1~R C12 P u ll- lo w RC7 RC8 RC9 RC10 RC11 RC12
T .G .1 T .G .2 T .G .3 T .G .4 T .G .5 T .G .6 T .G .7 T .G .8 T .G .9
T .G .1 0 T .G .1 1 T .G .1 2
RCOUT
IN RREF CREF
T im e r B
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Input/Output Ports There are 9 bidirectional input/output lines in the microcontroller, all located within port PA and PB. All of these I/O ports can be used for input and output operations. For input operation, these ports are non-latching, that is, the inputs must be ready at the T2 rising edge of the MOV A,[m] instruction. For output operation, all the data is latched and remains unchanged until the output latch is rewritten. Each I/O line has its own control register, known as PAC and PBC, to control the input/output configuration. With this control register, the pin status is either a CMOS output or a Schmitt trigger input, but can be reconfigured dynamically, under software control. To function as an input, the corresponding bit in the control register must be written with a 1. The input source also depends on the control register. If the control register bit is 1, the input will read the pad state. If the control register bit is 0, the contents of the latches will move to the internal bus. The latter is possible in the read-modify-write instruction. When setup as an output the output types are CMOS. After a device reset, the I/O ports will be initially all setup as inputs, and will therefore be in a high state if the configuration options have selected pull-high resistors, otherwise they will be in a floating condition. Each bit of these input/output latches can be set or cleared by the SET [m].i and CLR [m].i instructions. Some instructions first input data and then follow the output operations. For example, SET [m].i, CLR [m].i, CPL [m], CPLA [m] read the entire port states into the CPU, execute the defined operations (bit-operation), and then write the results back to the latches or the accumulator. Each line of port A has the capability of waking-up the device. Each line of port A and port B has a pull-high option. Once the pull-high option is selected, the I/O line will have a pull-high resistor connected. Otherwise, the pull-high resistors are absent. It should be noted that a non-pull-high I/O line operating in an input mode will be in a floating state. The PA0, PA1 and PA2 are pin-shared with INT0, INT1 and TMR pins, respectively. Pins PA0~PA3 and PA4~PA7 are pin-shared with RC1~RC4 and RC9~RC12, respectively. If configuration options select PA0~PA7 to be RC input pins, then the corresponding bits in the PA data register and PA control register will be unimplemented. It is recommended that unused or not bonded out I/O lines should be set as output pins using software instruction to avoid consuming power under input floating state.
VFD Driver
The device includes a VFD driver function to drive VFD panel high voltage filaments and buzzer. The microcontroller communicates serially with the VFD driver transmitting the display data into a 24-bit shift register within the driver. This VFD driver converts the shift register into VFD panel driving signals and makes the necessary voltage level shifting. The microcontroller will only transmit data to the VFD driver, no data is transmitted from the VFD driver to the microcontroller.
V C o n tr o l B it D a ta B u s W r ite C o n tr o l R e g is te r C h ip R e s e t R e a d C o n tr o l R e g is te r D CK S Q Q P u ll- h ig h
DD
I/O D a ta B it Q D CK S Q
W r ite D a ta R e g is te r
M U R e a d D a ta R e g is te r S y s te m W a k e -u p ( P A o n ly ) IN T 0 fo r P A 0 o n ly IN T 1 fo r P A 1 o n ly T M R fo r P A 2 o n ly
X O P0~O P7
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VFD Interface A five line interface exists between the microcontroller and the VFD driver as shown in the diagram. Data transmission between the microcontroller and the VFD interface is conducted via a three line interface using the CLK, DATA and STROBE lines. As data communication is only one way the microcontroller I/O pins must bet setup as outputs. The buzzer control input BZI will be transformed into a complementary pair of outputs BZO and BZO by a converter in the VFD driver. These complementary buzzer outputs will also be level shifted to a higher voltage by the converter. The VFD driver filament control input, F1, will also be shifted to a high voltage output called F1O, that can be used to switch the filaments on and off. 24-bit Shift Register/Latch Data transmitted from the microcontroller is transmitted serially and will be first written into a 24-bit shift register located within the VFD driver. These 24-bits are used to control the VFD panel segments, VFD0~VFD15, and grid, VFD16~VFD23, lines. The control method is as follows:
* Use the DATA and CLK lines to shift data into the
outputs will remain the same.
* Use the STROBE line to latch the shift-register data
to the VFD0~VFD23 outputs. When the STROBE line is high, the shift register data will be latched to the VFD lines. Note that the STROBE line is level and not edge triggered. The accompanying table shows the 24-bit shift register/latch function truth table: Clock Note: Strobe 0 1 1 1 Data X 0 1 1 VFD0 VFDn
No change No change 0 1 VFDn-1 VFDn-1
No change No change
X means dont care VFDn means VFD1~VFD23
Programming Considerations After power on all the I/O lines will be automatically setup as inputs. However as lines PB3~PB7 are used to drive the VFD and buzzer interface, they should be setup as outputs after power is applied to the device. Allowing the VFD interface control lines to be setup as inputs will create an incorrect VFD display and buzzer operation. It is advised that the configuration options select pull-high resistors to be connected to these lines to keep the lines at a fixed high level when power is initially applied and until the lines can be setup as outputs.
internal 24-bit shift register. Data is clocked into the shift-register on the positive clock edge. This data corresponds to the desired VFD0~VFD23 output display data. The VFD outputs will only change if the STROBE line is high. If the STROBE line is low, only the shift register data will be modified and the VFD
STROBE CLK DATA BZI F1
PB5 PB6 PB7 PB3 PB4 Pad Nam e
S h ift R e g is te r & L a tc h Level S h ifte r
VFD0 VFD23
C o m p le m e n t O u tp u t C o n v e rte r
BZO BZO F1O
VFD
D r iv e r
O u tp u ts
VFD Driver
CLK
DATA
STROBE
VFD0
VFD Display Control Timing Diagram Rev. 1.00 24 January 15, 2009
HT45R35V
Programming Example The following example shows how the VFD display data is programmed by the microcontroller. strobe equ pb.5 clk equ pb.6 data equ pb.7 data_2_register: ; send data to vfd driver mov a,024d ; shift register counter mov count,a clr strobe ; strobe = 0 data_2_register_1: clr clk ; clk = 0 set data ; data = 1 snz vfd_grid.7 clr data ; data = 0 rlc vfd_segl ; shift data to vfd[7:0] rlc vfd_segh ; shift data to vfd[15:8] rlc vfd_grid ; shift data to vfd[22:16] set clk ; clk = 1 (rising edge) sdz count jmp data_2_register_1 set strobe ; strobe = 1, vfd output ret
Low Voltage Reset - LVR The microcontroller provides a low voltage reset circuit in order to monitor the supply voltage of the device. If the supply voltage of the device is within the range 0.9V~VLVR, such as when changing a battery, the LVR will automatically reset the device internally. The LVR includes the following specifications:
* The low voltage (0.9V~VLVR) has to remain in its origi-
The relationship between VDD and VLVR is shown below.
VDD 5 .5 V V
OPR
5 .5 V
V 3 .0 V 2 .2 V
LVR
nal state for longer than tLVR. If the low voltage state does not exceed tLVR, the LVR will ignore it and will not perform a reset function.
* The LVR uses an OR function with the external RES
0 .9 V
Note:
signal to perform a chip reset.
V 5 .5 V
DD
VOPR is the voltage range for proper chip operation at 4MHz system clock.
V
LVR
LVR
D e te c t V o lta g e
0 .9 V 0V R e s e t S ig n a l
R eset *1
N o r m a l O p e r a tio n *2
R eset
Low Voltage Reset Note: *1: To make sure that the system oscillator has stabilized, the SST provides an extra delay of 1024 system clock pulses before starting the normal operation. *2: Since low voltage has to be maintained its original state for longer than tLVR, therefore a tLVR delay enters the reset mode. Rev. 1.00 25 January 15, 2009
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Options The following table shows the various options within the microcontroller. All of the options must be defined to ensure proper system functioning. No. 1 2 3 4 5 6 7 8 9 10 Function Wake up PA0~PA7 (bit option) Description None wake-up or wake-up
Pull high PA0~PA7, PB0 and PB3~PB7 (bit option) None pull-high or pull-high WDT clock source WDT CLRWDT LVR OSC INT0 trigger edge INT1 trigger edge I/O or RC connection pins WDTOSC or fSYS/4 Enable or disable 1 or 2 instructions Enable or disable Xtal mode or RC mode Disable, rising edge, falling edge or double edge Disable, rising edge, falling edge or double edge PA0 or RC1, PA1 or RC2, PA2 or RC3, PA3 or RC4, PA4 or RC9, PA5 or RC10, PA6 or RC11, PA7 or RC12
Application Circuits
R to F Application Circuit
VCC 10mF V
DD
VFD 0~VFD 23 PB0 F1O BZO BZO R R
sensor sensor
VO VDD Reset C ir c u it RES 0 .1 m F VSS
100kW 0 .1 m F
RC1 RC2 R
1 2
RC12 RREF RCOUT IN CREF
sensor
12 *R
OSC C ir c u it S e e O s c illa to r S e c tio n
OSC1 OSC2
*C
H T45R 35V
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C to F Application Circuit 1
VCC 10mF V
DD
VFD 0~VFD 23 PB0
VO VDD Reset C ir c u it RES 0 .1 m F VSS
F1O BZO BZO C C
sensor sensor
100kW 0 .1 m F
RC1 RC2 C
1 2
RC12 CREF RCOUT IN RREF
sensor
12 *C
OSC C ir c u it S e e O s c illa to r S e c tio n
OSC1 OSC2
*R
H T45R 35V
C to F Application Circuit 2
VCC 10mF V
DD
VFD 0~VFD 23 PB0 F1O BZO BZO Reset C ir c u it RC1 RC2 C C C
sensor sensor
VO VDD
100kW 0 .1 m F 0 .1 m F VSS RES
1 2
RC12
sensor
12
OSC C ir c u it S e e O s c illa to r S e c tio n
OSC1 OSC2
RCOUT IN RREF CREF H T45R 35V
*R
*C
Note: 1. The *R resistance and *C capacitance should be consideration for the frequency of RC OSC. 2. Rsensor1~Rsensor12 are the resistance sensors. 3. Csensor1~Csensor12 are the capacitance sensors.
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Instruction Set
Introduction Central to the successful operation of any microcontroller is its instruction set, which is a set of program instruction codes that directs the microcontroller to perform certain operations. In the case of Holtek microcontrollers, a comprehensive and flexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of programming overheads. For easier understanding of the various instruction codes, they have been subdivided into several functional groupings. Instruction Timing Most instructions are implemented within one instruction cycle. The exceptions to this are branch, call, or table read instructions where two instruction cycles are required. One instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8MHz system oscillator, most instructions would be implemented within 0.5ms and branch or call instructions would be implemented within 1ms. Although instructions which require one more cycle to implement are generally limited to the JMP, CALL, RET, RETI and table read instructions, it is important to realize that any other instructions which involve manipulation of the Program Counter Low register or PCL will also take one more cycle to implement. As instructions which change the contents of the PCL will imply a direct jump to that new address, one more cycle will be required. Examples of such instructions would be CLR PCL or MOV PCL, A. For the case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. Moving and Transferring Data The transfer of data within the microcontroller program is one of the most frequently used operations. Making use of three kinds of MOV instructions, data can be transferred from registers to the Accumulator and vice-versa as well as being able to move specific immediate data directly into the Accumulator. One of the most important data transfer applications is to receive data from the input ports and transfer data to the output ports. Arithmetic Operations The ability to perform certain arithmetic operations and data manipulation is a necessary feature of most microcontroller applications. Within the Holtek microcontroller instruction set are a range of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. Care must be taken to ensure correct handling of carry and borrow data when results exceed 255 for addition and less than 0 for subtraction. The increment and decrement instructions INC, INCA, DEC and DECA provide a simple means of increasing or decreasing by a value of one of the values in the destination specified. Logical and Rotate Operations The standard logical operations such as AND, OR, XOR and CPL all have their own instruction within the Holtek microcontroller instruction set. As with the case of most instructions involving data manipulation, data must pass through the Accumulator which may involve additional programming steps. In all logical data operations, the zero flag may be set if the result of the operation is zero. Another form of logical data manipulation comes from the rotate instructions such as RR, RL, RRC and RLC which provide a simple means of rotating one bit right or left. Different rotate instructions exist depending on program requirements. Rotate instructions are useful for serial port programming applications where data can be rotated from an internal register into the Carry bit from where it can be examined and the necessary serial bit set high or low. Another application where rotate data operations are used is to implement multiplication and division calculations. Branches and Control Transfer Program branching takes the form of either jumps to specified locations using the JMP instruction or to a subroutine using the CALL instruction. They differ in the sense that in the case of a subroutine call, the program must return to the instruction immediately when the subroutine has been carried out. This is done by placing a return instruction RET in the subroutine which will cause the program to jump back to the address right after the CALL instruction. In the case of a JMP instruction, the program simply jumps to the desired location. There is no requirement to jump back to the original jumping off point as in the case of the CALL instruction. One special and extremely useful set of branch instructions are the conditional branches. Here a decision is first made regarding the condition of a certain data memory or individual bits. Depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. These instructions are the key to decision making and branching within the program perhaps determined by the condition of certain input switches or by the condition of internal data bits.
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Bit Operations The ability to provide single bit operations on Data Memory is an extremely flexible feature of all Holtek microcontrollers. This feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the SET [m].i or CLR [m].i instructions respectively. The feature removes the need for programmers to first read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. This read-modify-write process is taken care of automatically when these bit operation instructions are used. Table Read Operations Data storage is normally implemented by using registers. However, when working with large amounts of fixed data, the volume involved often makes it inconvenient to store the fixed data in the Data Memory. To overcome this problem, Holtek microcontrollers allow an area of Program Memory to be setup as a table where data can be directly stored. A set of easy to use instructions provides the means by which this fixed data can be referenced and retrieved from the Program Memory. Other Operations In addition to the above functional instructions, a range of other instructions also exist such as the HALT instruction for Power-down operations and instructions to control the operation of the Watchdog Timer for reliable program operations under extreme electric or electromagnetic environments. For their relevant operations, refer to the functional related sections. Instruction Set Summary The following table depicts a summary of the instruction set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions. Table conventions: x: Bits immediate data m: Data Memory address A: Accumulator i: 0~7 number of bits addr: Program memory address
Mnemonic Arithmetic ADD A,[m] ADDM A,[m] ADD A,x ADC A,[m] ADCM A,[m] SUB A,x SUB A,[m] SUBM A,[m] SBC A,[m] SBCM A,[m] DAA [m] AND A,[m] OR A,[m] XOR A,[m] ANDM A,[m] ORM A,[m] XORM A,[m] AND A,x OR A,x XOR A,x CPL [m] CPLA [m] INCA [m] INC [m] DECA [m] DEC [m]
Description
Cycles
Flag Affected
Add Data Memory to ACC Add ACC to Data Memory Add immediate data to ACC Add Data Memory to ACC with Carry Add ACC to Data memory with Carry Subtract immediate data from the ACC Subtract Data Memory from ACC Subtract Data Memory from ACC with result in Data Memory Subtract Data Memory from ACC with Carry Subtract Data Memory from ACC with Carry, result in Data Memory Decimal adjust ACC for Addition with result in Data Memory Logical AND Data Memory to ACC Logical OR Data Memory to ACC Logical XOR Data Memory to ACC Logical AND ACC to Data Memory Logical OR ACC to Data Memory Logical XOR ACC to Data Memory Logical AND immediate Data to ACC Logical OR immediate Data to ACC Logical XOR immediate Data to ACC Complement Data Memory Complement Data Memory with result in ACC Increment Data Memory with result in ACC Increment Data Memory Decrement Data Memory with result in ACC Decrement Data Memory
1 1Note 1 1 1Note 1 1 1Note 1 1Note 1Note 1 1 1 1Note 1Note 1Note 1 1 1 1Note 1 1 1Note 1 1Note
Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV C Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z
Logic Operation
Increment & Decrement
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Mnemonic Rotate RRA [m] RR [m] RRCA [m] RRC [m] RLA [m] RL [m] RLCA [m] RLC [m] Data Move MOV A,[m] MOV [m],A MOV A,x Bit Operation CLR [m].i SET [m].i Branch JMP addr SZ [m] SZA [m] SZ [m].i SNZ [m].i SIZ [m] SDZ [m] SIZA [m] SDZA [m] CALL addr RET RET A,x RETI Table Read TABRDC [m] TABRDL [m] Miscellaneous NOP CLR [m] SET [m] CLR WDT CLR WDT1 CLR WDT2 SWAP [m] SWAPA [m] HALT Note: No operation Clear Data Memory Set Data Memory Clear Watchdog Timer Pre-clear Watchdog Timer Pre-clear Watchdog Timer Swap nibbles of Data Memory Swap nibbles of Data Memory with result in ACC Enter power down mode 1 1Note 1Note 1 1 1 1Note 1 1 None None None TO, PDF TO, PDF TO, PDF None None TO, PDF Read table (current page) to TBLH and Data Memory Read table (last page) to TBLH and Data Memory 2Note 2Note None None Jump unconditionally Skip if Data Memory is zero Skip if Data Memory is zero with data movement to ACC Skip if bit i of Data Memory is zero Skip if bit i of Data Memory is not zero Skip if increment Data Memory is zero Skip if decrement Data Memory is zero Skip if increment Data Memory is zero with result in ACC Skip if decrement Data Memory is zero with result in ACC Subroutine call Return from subroutine Return from subroutine and load immediate data to ACC Return from interrupt 2 1Note 1note 1Note 1Note 1Note 1Note 1Note 1Note 2 2 2 2 None None None None None None None None None None None None None Clear bit of Data Memory Set bit of Data Memory 1Note 1Note None None Move Data Memory to ACC Move ACC to Data Memory Move immediate data to ACC 1 1Note 1 None None None Rotate Data Memory right with result in ACC Rotate Data Memory right Rotate Data Memory right through Carry with result in ACC Rotate Data Memory right through Carry Rotate Data Memory left with result in ACC Rotate Data Memory left Rotate Data Memory left through Carry with result in ACC Rotate Data Memory left through Carry 1 1Note 1 1Note 1 1Note 1 1Note None None C C None None C C Description Cycles Flag Affected
1. For skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution. 3. For the CLR WDT1 and CLR WDT2 instructions the TO and PDF flags may be affected by the execution status. The TO and PDF flags are cleared after both CLR WDT1 and CLR WDT2 instructions are consecutively executed. Otherwise the TO and PDF flags remain unchanged.
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Instruction Definition
ADC A,[m] Description Operation Affected flag(s) ADCM A,[m] Description Operation Affected flag(s) ADD A,[m] Description Operation Affected flag(s) ADD A,x Description Operation Affected flag(s) ADDM A,[m] Description Operation Affected flag(s) AND A,[m] Description Operation Affected flag(s) AND A,x Description Operation Affected flag(s) ANDM A,[m] Description Operation Affected flag(s) Add Data Memory to ACC with Carry The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the Accumulator. ACC ACC + [m] + C OV, Z, AC, C Add ACC to Data Memory with Carry The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the specified Data Memory. [m] ACC + [m] + C OV, Z, AC, C Add Data Memory to ACC The contents of the specified Data Memory and the Accumulator are added. The result is stored in the Accumulator. ACC ACC + [m] OV, Z, AC, C Add immediate data to ACC The contents of the Accumulator and the specified immediate data are added. The result is stored in the Accumulator. ACC ACC + x OV, Z, AC, C Add ACC to Data Memory The contents of the specified Data Memory and the Accumulator are added. The result is stored in the specified Data Memory. [m] ACC + [m] OV, Z, AC, C Logical AND Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical AND operation. The result is stored in the Accumulator. ACC ACC AND [m] Z Logical AND immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical AND operation. The result is stored in the Accumulator. ACC ACC AND x Z Logical AND ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical AND operation. The result is stored in the Data Memory. [m] ACC AND [m] Z
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CALL addr Description Subroutine call Unconditionally calls a subroutine at the specified address. The Program Counter then increments by 1 to obtain the address of the next instruction which is then pushed onto the stack. The specified address is then loaded and the program continues execution from this new address. As this instruction requires an additional operation, it is a two cycle instruction. Stack Program Counter + 1 Program Counter addr None Clear Data Memory Each bit of the specified Data Memory is cleared to 0. [m] 00H None Clear bit of Data Memory Bit i of the specified Data Memory is cleared to 0. [m].i 0 None Clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. WDT cleared TO 0 PDF 0 TO, PDF Pre-clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT2 and must be executed alternately with CLR WDT2 to have effect. Repetitively executing this instruction without alternately executing CLR WDT2 will have no effect. WDT cleared TO 0 PDF 0 TO, PDF Pre-clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Repetitively executing this instruction without alternately executing CLR WDT1 will have no effect. WDT cleared TO 0 PDF 0 TO, PDF
Operation Affected flag(s) CLR [m] Description Operation Affected flag(s) CLR [m].i Description Operation Affected flag(s) CLR WDT Description Operation
Affected flag(s) CLR WDT1 Description
Operation
Affected flag(s) CLR WDT2 Description
Operation
Affected flag(s)
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CPL [m] Description Operation Affected flag(s) CPLA [m] Description Complement Data Memory Each bit of the specified Data Memory is logically complemented (1s complement). Bits which previously contained a 1 are changed to 0 and vice versa. [m] [m] Z Complement Data Memory with result in ACC Each bit of the specified Data Memory is logically complemented (1s complement). Bits which previously contained a 1 are changed to 0 and vice versa. The complemented result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC [m] Z Decimal-Adjust ACC for addition with result in Data Memory Convert the contents of the Accumulator value to a BCD ( Binary Coded Decimal) value resulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of 6 will be added to the high nibble. Essentially, the decimal conversion is performed by adding 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C flag may be affected by this instruction which indicates that if the original BCD sum is greater than 100, it allows multiple precision decimal addition. [m] ACC + 00H or [m] ACC + 06H or [m] ACC + 60H or [m] ACC + 66H C Decrement Data Memory Data in the specified Data Memory is decremented by 1. [m] [m] - 1 Z Decrement Data Memory with result in ACC Data in the specified Data Memory is decremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC [m] - 1 Z Enter power down mode This instruction stops the program execution and turns off the system clock. The contents of the Data Memory and registers are retained. The WDT and prescaler are cleared. The power down flag PDF is set and the WDT time-out flag TO is cleared. TO 0 PDF 1 TO, PDF
Operation Affected flag(s) DAA [m] Description
Operation
Affected flag(s) DEC [m] Description Operation Affected flag(s) DECA [m] Description Operation Affected flag(s) HALT Description
Operation Affected flag(s)
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INC [m] Description Operation Affected flag(s) INCA [m] Description Operation Affected flag(s) JMP addr Description Increment Data Memory Data in the specified Data Memory is incremented by 1. [m] [m] + 1 Z Increment Data Memory with result in ACC Data in the specified Data Memory is incremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC [m] + 1 Z Jump unconditionally The contents of the Program Counter are replaced with the specified address. Program execution then continues from this new address. As this requires the insertion of a dummy instruction while the new address is loaded, it is a two cycle instruction. Program Counter addr None Move Data Memory to ACC The contents of the specified Data Memory are copied to the Accumulator. ACC [m] None Move immediate data to ACC The immediate data specified is loaded into the Accumulator. ACC x None Move ACC to Data Memory The contents of the Accumulator are copied to the specified Data Memory. [m] ACC None No operation No operation is performed. Execution continues with the next instruction. No operation None Logical OR Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical OR operation. The result is stored in the Accumulator. ACC ACC OR [m] Z
Operation Affected flag(s) MOV A,[m] Description Operation Affected flag(s) MOV A,x Description Operation Affected flag(s) MOV [m],A Description Operation Affected flag(s) NOP Description Operation Affected flag(s) OR A,[m] Description Operation Affected flag(s)
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OR A,x Description Operation Affected flag(s) ORM A,[m] Description Operation Affected flag(s) RET Description Operation Affected flag(s) RET A,x Description Operation Affected flag(s) RETI Description Logical OR immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical OR operation. The result is stored in the Accumulator. ACC ACC OR x Z Logical OR ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical OR operation. The result is stored in the Data Memory. [m] ACC OR [m] Z Return from subroutine The Program Counter is restored from the stack. Program execution continues at the restored address. Program Counter Stack None Return from subroutine and load immediate data to ACC The Program Counter is restored from the stack and the Accumulator loaded with the specified immediate data. Program execution continues at the restored address. Program Counter Stack ACC x None Return from interrupt The Program Counter is restored from the stack and the interrupts are re-enabled by setting the EMI bit. EMI is the master interrupt global enable bit. If an interrupt was pending when the RETI instruction is executed, the pending Interrupt routine will be processed before returning to the main program. Program Counter Stack EMI 1 None Rotate Data Memory left The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. [m].(i+1) [m].i; (i = 0~6) [m].0 [m].7 None Rotate Data Memory left with result in ACC The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.(i+1) [m].i; (i = 0~6) ACC.0 [m].7 None
Operation Affected flag(s) RL [m] Description Operation Affected flag(s) RLA [m] Description
Operation Affected flag(s)
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RLC [m] Description Operation Rotate Data Memory left through Carry The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into bit 0. [m].(i+1) [m].i; (i = 0~6) [m].0 C C [m].7 C Rotate Data Memory left through Carry with result in ACC Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.(i+1) [m].i; (i = 0~6) ACC.0 C C [m].7 C Rotate Data Memory right The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into bit 7. [m].i [m].(i+1); (i = 0~6) [m].7 [m].0 None Rotate Data Memory right with result in ACC Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0 rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.i [m].(i+1); (i = 0~6) ACC.7 [m].0 None Rotate Data Memory right through Carry The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. [m].i [m].(i+1); (i = 0~6) [m].7 C C [m].0 C Rotate Data Memory right through Carry with result in ACC Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.i [m].(i+1); (i = 0~6) ACC.7 C C [m].0 C
Affected flag(s) RLCA [m] Description
Operation
Affected flag(s) RR [m] Description Operation Affected flag(s) RRA [m] Description
Operation Affected flag(s) RRC [m] Description Operation
Affected flag(s) RRCA [m] Description
Operation
Affected flag(s)
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SBC A,[m] Description Subtract Data Memory from ACC with Carry The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ACC - [m] - C OV, Z, AC, C Subtract Data Memory from ACC with Carry and result in Data Memory The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. [m] ACC - [m] - C OV, Z, AC, C Skip if decrement Data Memory is 0 The contents of the specified Data Memory are first decremented by 1. If the result is 0 the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. [m] [m] - 1 Skip if [m] = 0 None Skip if decrement Data Memory is zero with result in ACC The contents of the specified Data Memory are first decremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. ACC [m] - 1 Skip if ACC = 0 None Set Data Memory Each bit of the specified Data Memory is set to 1. [m] FFH None Set bit of Data Memory Bit i of the specified Data Memory is set to 1. [m].i 1 None
Operation Affected flag(s) SBCM A,[m] Description
Operation Affected flag(s) SDZ [m] Description
Operation Affected flag(s) SDZA [m] Description
Operation Affected flag(s) SET [m] Description Operation Affected flag(s) SET [m].i Description Operation Affected flag(s)
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SIZ [m] Description Skip if increment Data Memory is 0 The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. [m] [m] + 1 Skip if [m] = 0 None Skip if increment Data Memory is zero with result in ACC The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. ACC [m] + 1 Skip if ACC = 0 None Skip if bit i of Data Memory is not 0 If bit i of the specified Data Memory is not 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is 0 the program proceeds with the following instruction. Skip if [m].i 0 None Subtract Data Memory from ACC The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ACC - [m] OV, Z, AC, C Subtract Data Memory from ACC with result in Data Memory The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. [m] ACC - [m] OV, Z, AC, C Subtract immediate data from ACC The immediate data specified by the code is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ACC - x OV, Z, AC, C
Operation Affected flag(s) SIZA [m] Description
Operation Affected flag(s) SNZ [m].i Description
Operation Affected flag(s) SUB A,[m] Description
Operation Affected flag(s) SUBM A,[m] Description
Operation Affected flag(s) SUB A,x Description
Operation Affected flag(s)
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SWAP [m] Description Operation Affected flag(s) SWAPA [m] Description Operation Affected flag(s) SZ [m] Description Swap nibbles of Data Memory The low-order and high-order nibbles of the specified Data Memory are interchanged. [m].3~[m].0 [m].7 ~ [m].4 None Swap nibbles of Data Memory with result in ACC The low-order and high-order nibbles of the specified Data Memory are interchanged. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC.3 ~ ACC.0 [m].7 ~ [m].4 ACC.7 ~ ACC.4 [m].3 ~ [m].0 None Skip if Data Memory is 0 If the contents of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. Skip if [m] = 0 None Skip if Data Memory is 0 with data movement to ACC The contents of the specified Data Memory are copied to the Accumulator. If the value is zero, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. ACC [m] Skip if [m] = 0 None Skip if bit i of Data Memory is 0 If bit i of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. Skip if [m].i = 0 None Read table (current page) to TBLH and Data Memory The low byte of the program code (current page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] program code (low byte) TBLH program code (high byte) None Read table (last page) to TBLH and Data Memory The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] program code (low byte) TBLH program code (high byte) None
Operation Affected flag(s) SZA [m] Description
Operation Affected flag(s) SZ [m].i Description
Operation Affected flag(s) TABRDC [m] Description Operation Affected flag(s) TABRDL [m] Description Operation Affected flag(s)
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XOR A,[m] Description Operation Affected flag(s) XORM A,[m] Description Operation Affected flag(s) XOR A,x Description Operation Affected flag(s) Logical XOR Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR operation. The result is stored in the Accumulator. ACC ACC XOR [m] Z Logical XOR ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR operation. The result is stored in the Data Memory. [m] ACC XOR [m] Z Logical XOR immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical XOR operation. The result is stored in the Accumulator. ACC ACC XOR x Z
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Package Information
52-pin QFP (14mm14mm) Outline Dimensions
C D 39 27 G H
I 40 26 F A B E
52
14 K J 1 13
Symbol A B C D E F G H I J K a
Dimensions in mm Min. 17.3 13.9 17.3 13.9 3/4 3/4 2.5 3/4 3/4 0.73 0.1 0 Nom. 3/4 3/4 3/4 3/4 1 0.4 3/4 3/4 0.1 3/4 3/4 3/4 Max. 17.5 14.1 17.5 14.1 3/4 3/4 3.1 3.4 3/4 1.03 0.2 7
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Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Taipei Sales Office) 4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor Inc. (Shanghai Sales Office) G Room, 3 Floor, No.1 Building, No.2016 Yi-Shan Road, Minhang District, Shanghai, China 201103 Tel: 86-21-5422-4590 Fax: 86-21-5422-4705 http://www.holtek.com.cn Holtek Semiconductor Inc. (Shenzhen Sales Office) 5F, Unit A, Productivity Building, Gaoxin M 2nd, Middle Zone Of High-Tech Industrial Park, ShenZhen, China 518057 Tel: 86-755-8616-9908, 86-755-8616-9308 Fax: 86-755-8616-9722 Holtek Semiconductor Inc. (Beijing Sales Office) Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031 Tel: 86-10-6641-0030, 86-10-6641-7751, 86-10-6641-7752 Fax: 86-10-6641-0125 Holtek Semiconductor Inc. (Chengdu Sales Office) 709, Building 3, Champagne Plaza, No.97 Dongda Street, Chengdu, Sichuan, China 610016 Tel: 86-28-6653-6590 Fax: 86-28-6653-6591 Holtek Semiconductor (USA), Inc. (North America Sales Office) 46729 Fremont Blvd., Fremont, CA 94538 Tel: 1-510-252-9880 Fax: 1-510-252-9885 http://www.holtek.com
Copyright O 2009 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holteks products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.
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